This invention mainly relates to a semiconductor memory device, such as, a dynamic random access memory (DRAM), which is suitable for high integration and high capacity, and in particular, to a semiconductor memory device having a memory structure in which cells are arranged with cell arrangement pattern of the folded bit line system of one transistor/one capacitor structure.
Recently, high integration and high capacity of a semiconductor memory device have developed rapidly with an advancement of miniaturization in the semiconductormanufacturing field.
In such integration with respect to an integrated circuit of the semiconductor memory device, a cell layout of a memory cell array having the one transistor/one capacitor structure is suitable for the miniaturization.
Further, the cell arrangement pattern of the folded bit line system generally has been applied for the cell layout to achieve large area and high speed.
Alternatively, a variety of cell layouts have been suggested other than the above-mentioned cell layout.
In a conventional memory cell structure illustrated in FIG. 1, cells are arranged with a cell arrangement pattern of the known 1/2 pitch type folded bit line system of one transistor/one capacitor structure.
In such a memory structure, a plurality of bit lines 102a are placed in a parallel horizontal direction while a plurality of word lines 11a are placed in a vertical direction. Thus, the bit lines 102a and word lines 101a are crossed to each other.
With this structure, a plurality of device region patterns 100a are arranged in a direction parallel to the bit line. In this event, each of the device region patterns 100a is formed in a rectangular shape.
Further, each of the device region patterns 100a has wiring patterns 104a in the both ends and a wiring pattern 103a in a center portion. In this condition, a capacitor contact 106a is arranged in each of the wiring patterns 104a in the device region pattern 100a while a bit contact 105a is arranged in the wiring pattern 103a on the bit line 102a.
In this case, the wiring pattern 103a is patterned and arranged to connect the bit contact 105a with a diffusion layer. Moreover, the wiring pattern 104a is patterned and arranged to connect the capacitor contact 106a with a diffusion layer.
Under this condition, the device region patterns 100a are alternately arranged at every 1/2 pitch in the direction parallel to the bit line 102a. For instance, the device region patterns 110, 111 and 112, each of which has a width w1, are formed as illustrated in FIG. 1.
In the cell layout illustrated in FIG. 1, when attention is paid for the device region pattern 110 and spaces between adjacent device region patterns 111,112 and the device region pattern 110 are considered, the device region pattern 111 is closest to the device region pattern 110 while the device region pattern 112 is further apart from the device region pattern 110 in comparison with the device region pattern 111.
In this case, a distance between the device region patterns 110 and 111 is equal to a space d while a distance between the device region patterns 110 and 112 is equal to a space s.
The space s is considerably large as compared to the space d. When the space d and the space s are compared to each other, the space d becomes a minimum distance to be formed and processed.
In contrast, the space s is considerably larger than the space d and has a margin in comparison with the minimum space. Consequently, a wasteful area inevitably takes place in the cell layout.
To solve the above-mentioned problem, suggestion has been made about another cell layout in Japanese Patent Publication (JP-B) No. Hei. 7-120714.
In this cell layout, high density of the device region patterns can be achieved by reducing the wasteful region in the memory cell structure to further enhance pattern density of the device region patterns.
In another conventional memory cell structure illustrated in FIG. 2, cells are arranged with cell arrangement pattern of the known 1/4 pitch type folded bit line system for achieving the high density of the device region patterns.
In such a memory structure, a plurality of bit lines 102b are placed in a parallel direction while a plurality of word lines 101b are placed in a vertical direction in the same manner as the structure illustrated in FIG. 1. Thus, the bit lines 102b and the word lines.101b are crossed to each other.
With this structure, a plurality of device region patterns 100b are inclined for the bit lines 102b. In this event, each of the device region patterns 100b is formed in a rectangular shape. Herein, both ends of the device region pattern 100b are perpendicularly shaped, as illustrated in FIG. 2.
Further, each of the device region patterns 100b has wiring patterns 104b in both ends and a wiring pattern 103b in a center portion. In this condition, a capacitor contact 106b is arranged in each of the wiring patterns 104b in the device region pattern 100b while a bit contact 105b is arranged in the wiring pattern 103b on the bit line 102b in the device region pattern 100b.
In this case, the wiring pattern 103b is patterned and arranged to connect the bit contact 105b with a diffusion layer. Moreover, the wiring pattern 104b is patterned and arranged to connect the capacitor contact 106b with a diffusion layer.
Under this condition, the device region patterns 100b are alternately arranged at every 1/4 pitch on the basis of the bit lines 102b. For instance, the device region patterns 113,114 and 115, each of which has a width w2, are formed as illustrated in FIG. 2.
In the cell layout illustrated in FIG. 2, when attention is paid for the device region pattern 113, and spaces between adjacent device region patterns 114, 115 and the device region pattern 113 are considered, the device region pattern 114 is closest to the device region pattern 113.
In this case, a distance between the device region patterns 113 and 114 is equal to a space d while a distance between the device region patterns 113 and 115 is equal to a space d'. This space d' is considerably small in comparison with the space s illustrated in FIG. 1. Consequently, field integration is increased in the cell layout illustrated in FIG. 2.
In this case, when the cell layouts of the memory cell structures illustrated in FIGS. 1 and 2 are compared to each other, it is assumed that the cell sizes are identical to each other.
Under this circumstance, when the space d' of the 1/4 pitch type is equal to the space d of the 1/2 pitch type (namely, d =d'), the width w2 of each device region pattern 113, 114 and 115 of the 1/4 pitch type exceeds the width w1 of each device region 110, 111 and 112 of the 1/2 pitch type (namely, w1&lt;w2).
On the other hand, when the widths of the respective device region patterns are identical to each other (w1 =w2), the space d' of the 1/4 pitch type exceeds the space d of the 1/2 pitch type (namely, d' &gt;d).
Alternatively, when the spaces and widths of the respective device region patterns are identical to each other, the cell size can be reduced in the cell layout of the 1/4 pitch.
In the meanwhile, there are Japanese Unexamined Patent Publications No. Hei. 2-226763 and No. Hei 4-65872 as the other conventional techniques related to the semiconductor memory device.
In the case of the semiconductor memory device having the memory structure due to the cell layout of the 1/4 pitch type, when attention is paid for the wiring pattern of the capacitor contact for connecting with the diffusion layer, the diffusion layer is arranged with the minimum space same as the memory cell structure due to the cell structure of the 1/2 pitch type.
However, when shrinkage and deviation occur during the formation of the pattern in such a structure, the diffusion layer of the capacitor contact is not sufficiently formed.
Consequently, the contacting area of the diffusion layer and the wiring pattern of the capacitor contact is inevitably increased. As a result, contact resistance is also increased.